1. Field of the Invention
The present invention relates to semiconductor integrated circuitry. More particularly, the present invention relates to a voltage sensing circuit to sense the voltage level of an input voltage signal for integrated circuitry.
2. Description of the Related Art
Usually, voltage-sensing circuits are utilized to sense power up and power down operations in the application of integrated circuitry applications, and, accordingly, enable other circuits to perform the corresponding actions if required. In the power up mode, the voltage sensing circuit receives an input voltage signal, generating an enable output signal when the input voltage signal has exceeded a predetermined threshold level. Before that, when the input voltage signal is below the predetermined threshold level, the voltage sensing circuit generates a disable signal to disable core portions of the integrated circuit so as to prevent uncertain functioning due to either voltage level or system noise. In the power down mode, the voltage sensing circuit generates the disable output signal when the input power voltage falls below the predetermined threshold level, thereby assuring that certain core portions of the circuit are disabled when the power supply goes below the predetermined threshold level and preventing uncertain functioning due to voltage level or system noise.
However, conventional voltage sensing circuits have typically consumed too much power during operation. Such high power consumption is disadvantageous for application in low power consumption products such as notebook computers, personal digital assistants, etc. Therefore, U.S. Pat. No. 5,181,187 discloses a low power voltage sensing circuit as shown in FIG. 1. The voltage sensing circuit of FIG. 1 comprises two PMOS transistors 10 and 13, two reference voltages 11 and 15, a voltage drop circuit 12 and an NMOS transistor 14.
In FIG. 1, the PMOS 10 is configured with one source/drain receiving an input voltage signal V.sub.CC, another source/drain connected to a sensing node 17 at which a sensing voltage V.sub.SEN is generated, and a gate connected to the reference voltage 11. The voltage drop circuit 12 receives the input voltage signal V.sub.CC and generates a voltage signal V.sub.1 that is lower in voltage than the input voltage signal V.sub.CC. The PMOS transistor 13 is configured with one source/drain receiving the voltage signal V.sub.1, another source/drain connected to the gate of the NMOS transistor 14, and its gate connected to the first reference voltage 11. The NMOS transistor 14 has one source/drain region connected to the sensing node 17, and another source/drain connected to the second reference voltage 15.
Referring to FIG. 1, an embodiment of U.S. Pat. No. 5,181,187 is exemplified in which the first reference voltage 11 and the second reference voltage 15 are simply the ground potentials, the voltage drop circuit 12 being implemented by means of PMOS transistor 16 having one source/drain receiving said input voltage signal V.sub.CC and another source/drain tied to its gate.
Accordingly, the voltage sensing circuit of FIG. 1 can produce low current conduction and thus lower power consumption by adjusting the channel width of the PMOS transistor 10 to be greater than the channel width of the NMOS transistor 14. However, at least four MOS transistors are required for the conventional voltage sensing circuit.